A Low Power FIR Filter Design Technique Using Dynamic Reduced Signal Representation

While arithmetic circuits using 2’s complement representation are easy to implement, it is well-known that the sign-extension bits of a 2’s complement number cause high switching activity in digital arithmetic circuits. Such switching is undesirable in low power applications. In this work, we exploit the sign-extension property of a 2’s complement number and propose a reduced representation of 2’s complement numbers to avoid sign-extension. Instead of having the high switching activity at the MSB side of the datapath, the proposed number representation avoids switching of the MSBs altogether, and therefore reduces the power dissipation in digital arithmetic circuits. With the proposed technique, the maximum magnitude of a 2’s complement number is detected and a reduced representation is dynamically generated to represent the signal. There is a constant error introduced by the reduced representation and such error is compensated accordingly. The proposed signal representation is particularly useful in digital filters where the coefficients are slowly varying and have small magnitudes. Our experimental results have shown a 38% power saving using the proposed technique.